Switching point detection circuit and semiconductor device using the same

ABSTRACT

A switching point detection circuit for detecting a switching point according to a fabrication condition of MOS transistor, includes a reference voltage generation unit for generating a reference voltage, a first CMOS inverter, in which an NMOS transistor is dominant for the reference voltage, receiving the reference voltage and a second CMOS inverter, in which a PMOS transistor is dominant for the reference voltage, receiving the reference voltage.

BACKGROUND

[0001] 1. Technical Field

[0002] A switching point detection circuit for detecting a switchingpoint according to a fabrication condition of a MOS transistor of asemiconductor device is disclosed.

[0003] 2. Description of The Related Art

[0004] When an input voltage signal for a CMOS inverter is transitedfrom a logic high level, e.g. 3.3 V, to a logic low level, e.g. 0 V, orfrom a logic low level, e.g. 0 V, to a logic high level, e.g. 3.3 V, ina semiconductor device, it is important that output voltage signals fromthe CMOS inverter have a symmetric voltage characteristic. Therefore,the CMOS inverter is generally designed with which the output voltagesignal is switched from a logic high level to a logic low level or froma logic low level to a logic high level when the voltage level of theinput voltage signal becomes a half level of the driving voltage of theCMOS inverter.

[0005] However, an MOS transistor may be fabricated in a differentmanner from that of a designed MOS transistor due to various conditionsin the semiconductor fabrication process. When the MOS transistor isoptimally fabricated to have the same condition with the designed MOStransistor, the MOS transistor is marked with ‘N’, which means a normaloperation. If the MOS transistor is fabricated to have a fasteroperation than the designed MOS transistor, the MOS transistor is markedwith ‘F’, which means a fast operation. Also, if the MOS transistor isfabricated to have a slower operation than the designed MOS transistor,the MOS transistor is marked with ‘S’, which means a slow operation. Theslower operation or the faster operation means whether a current flowingbetween source and drain in the MOS transistor is high or low when aconstant voltage is applied to a gate thereof.

[0006] The characteristic of the MOS transistor having the fasteroperation or the slower operation is determined by conditions of asemiconductor fabrication process, such as a doping density in asource/drain region, channel width and length and the like, which may bedifferently fabricated from the designed MOS transistor.

[0007] Hereinafter, a fabrication condition of a PMOS transistor and anNMOS transistor is marked with ‘N’, ‘F’ and ‘S’. For example, when thePMOS transistor is fabricated to have same condition with the designedPMOS transistor and the NMOS transistor is fabricated to have the fasteroperation than that of the designed NMOS transistor, the MOS transistorsare marked with ‘PNNF’.

[0008]FIG. 1A is a circuit diagram illustrating a typical CMOS inverter.

[0009] As shown, the typical CMOS inverter consists of a PMOS transistorP1 for outputting a power supply voltage VDD as an output voltage signalVout when an input signal is a low level voltage signal and an NMOStransistor for outputting a ground voltage VSS as an output voltagesignal Vout when an input signal is a high level voltage signal.

[0010] An operation characteristic of the CMOS inverter may be variedaccording to fabrication conditions, such as a power supply voltage, atemperature and the like. Since the MOS transistors P1 and N1 in theinverter may be differently fabricated from the designed MOS transistorsdue to the fabrication conditions, an operation characteristic of theinverter may be severely varied.

[0011]FIG. 1B is a waveform illustrating switching points of theinverter of FIG. 1 according to the fabrication conditions of the MOStransistor.

[0012] As shown, the CMOS inverter should be designed to switch theoutputs at a half supply voltage VDD/2 such a case of ‘a’ waveform.However, when the NMOS transistor N1 may be fabricated with ‘N’ and thePMOS transistor P1 may be fabricated with ‘F’ according to fabricationconditions, the CMOS inverter has a switching operation characteristicof a waveform ‘b’ in FIG. 1B. Also, when the NMOS transistor N1 isfabricated with ‘F’ and the PMOS transistor P1 is fabricated with ‘N’,the CMOS inverter has a switching operation characteristic of a waveform‘c’ in FIG. 1B.

[0013] If the operation characteristic of the PMOS and NMOS transistorsis varied according to the MOS transistor fabrication conditions, anoperation characteristic of the CMOS inverter is varied. Therefore, ifthis CMOS inverter is applied to an integrated circuit IC, operationreliability of the IC cannot be secured.

[0014] Accordingly, in order to secure a stable operation characteristicof the inverter regardless of the MOS transistor fabrication conditions,a circuit capable of adjusting the switching point of the inverter bydetecting the MOS transistor fabrication conditions is needed.

SUMMARY OF THE DISCLOSURE

[0015] A detection circuit detecting a switching point of an inverter ina semiconductor device is disclosed.

[0016] A disclosed switching point detection circuit for detecting aswitching point according to the fabrication condition of MOS transistorcomprises: a reference voltage generation unit for generating areference voltage; a first CMOS inverter, in which an NMOS transistor isdominant for the reference voltage, receiving the reference voltage; anda second CMOS inverter, in which a PMOS transistor is dominant for thereference voltage, receiving the reference voltage

[0017] Another disclosed switching point detection circuit for detectinga switching point according to a fabrication condition of MOS transistorcomprises: a reference voltage generation unit for generating a firstreference voltage, which is higher than a half power supply voltage, anda second reference voltage, which is lower than a half power supplyvoltage; a first CMOS inverter receiving the first reference voltage,having a switching point at the half power supply voltage; and a secondCMOS inverter receiving the second reference voltage and having aswitching point at the half power supply voltage.

[0018] A disclosed semiconductor device comprises: a buffering means forbuffering an input signal; a switching point detection means fordetecting switching point variation of a CMOS inverter according to afabrication condition of a MOS transistor; and a delay means fordelaying the input signal under control of the switching point detectionmeans.

[0019] Another disclosed semiconductor device comprises: a switchingpoint detection means for detecting switching point variation of a CMOSinverter according to a fabrication condition of a MOS transistor,including: a reference voltage generation unit for generating areference voltage; a first CMOS inverter, in which an NMOS transistor isdominant for the reference voltage, receiving the reference voltage; anda second CMOS inverter, in which a PMOS transistor is dominant for thereference voltage, receiving the reference voltage; a first multiplexerfor selectively outputting a power supply voltage or an input signalaccording to an output signal of the first CMOS inverter; a secondmultiplexer for selectively outputting a power supply voltage or aninput signal according to an output signal of the second CMOS inverter;a third CMOS inverter for inverting the input signal; a first pull-upmeans for performing a pull-up operation for an output of the third CMOSinverter according to an output signal of the first multiplexer; and asecond pull-up means for performing a pull-up operation for an output ofthe third CMOS inverter according to an output signal of the secondmultiplexer.

[0020] A disclosed semiconductor memory device comprises: a switchingpoint detection means for detecting switching point variation of a CMOSinverter according to a fabrication condition of a MOS transistor,includes: a reference voltage generation unit for generating a firstreference voltage, which is higher than a half power supply voltage, anda second reference voltage, which is lower than a half power supplyvoltage; a first CMOS inverter receiving the first reference voltage,having a switching point at the half power supply voltage; and a secondCMOS inverter receiving the second reference voltage and having aswitching point at the half power supply voltage; a first multiplexerfor selectively outputting a power supply voltage or an input signalaccording to an output signal of the first CMOS inverter; a secondmultiplexer for selectively outputting a power supply voltage or aninput signal according to an output signal of the second CMOS inverter;a third CMOS inverter for inverting the input signal; a first pull-upmeans for performing a pull-up operation for an output of the third CMOSinverter according to an output signal of the first multiplexer; and asecond pull-up means for performing a pull-up operation for an output ofthe third CMOS inverter according to an output signal of the secondmultiplexer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features of the disclosed circuits anddevices will become apparent from the following description of preferredembodiments taken in conjunction with the accompanying drawings,wherein:

[0022]FIG. 1A is a circuit diagram illustrating a typical CMOS inverter;

[0023]FIG. 1B is a waveform illustrating switching points of theinverter of FIG. 1;

[0024]FIG. 2A is a circuit diagram illustrating a switching pointdetection circuit in accordance with the preferred embodiment;

[0025]FIGS. 2B and 2C are waveforms illustrating a switching point ofthe detection circuit of FIG. 2A;

[0026]FIG. 3 is a diagram showing a logic table representing operationconditions of the switching point detection circuit of FIG. 2A;

[0027]FIG. 4 is a circuit diagram illustrating another switching pointdetection circuit capable of generating a different reference voltage;

[0028]FIGS. 5 and 6 are circuit diagrams illustrating another switchingpoint detection circuits;

[0029]FIGS. 7A to 7D are circuit diagrams showing methods for variouslygenerating the reference voltage;

[0030]FIGS. 8A and 8B are schematic diagrams illustrating switchingpoint detection circuits having a differential amplifier;

[0031]FIGS. 8C to 8F are circuit diagrams illustrating the differentialamplifier commonly applied in FIGS. 8A and 8B;

[0032]FIG. 9A is a circuit diagram showing a conventional input buffer;

[0033]FIG. 9B is a circuit diagram illustrating an input buffer having adisclosed switching point detection circuit;

[0034]FIG. 10 is a circuit diagram illustrating a disclosedsemiconductor device having a switching point detection circuit;

[0035]FIG. 11 is a waveform illustrating an operation of thesemiconductor device of FIG. 10;

[0036]FIG. 12A is a circuit diagram illustrating a semiconductor device,in which a long line having a high load is coupled to an input signal ofthe input buffer;

[0037]FIG. 12B is a circuit diagram illustrating a semiconductor device,in which a long line having a high load is coupled to an output signalof the output buffer; and

[0038]FIG. 12C is a waveform showing operations of the semiconductordevices illustrated in FIGS. 12A and 12B.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0039] Hereinafter, a semiconductor device having a detection circuitfor detecting a switching point of an inverter according to MOStransistor fabrication conditions in order to secure a stable operationcharacteristic of the semiconductor will be described in detailreferring to the accompanying drawings.

[0040]FIG. 2A is a circuit diagram illustrating a switching pointdetection circuit for detecting the switching point according to the MOStransistor fabrication conditions.

[0041] As shown, the switching point detection circuit includes areference voltage generator 10, a first inverter 20 and a secondinverter 30. The reference voltage generator 10 includes a firstresistance R1 and a second resistance R2 coupled in series between apower supply voltage VDD and a ground voltage VSS and a voltage dividedby the first and second resistances R1 and R2 is used as a referencevoltage Vref generated from a junction node of the first and secondresistances R1 and R2. Since the resistance is not sensitive forfabrication conditions, variation of the reference voltage Vref is notlarge.

[0042] The first inverter 20 is fabricated by which an NMOS transistorMN1 is dominant and the second inverter 30 is fabricated by which a PMOStransistor MP2 is dominant by adjusting channel width or length of theNMOS or PMOS transistor.

[0043]FIGS. 2B and 2C are waveforms illustrating a switching point ofthe detection circuit in FIG. 2A.

[0044] Hereinafter, an operation of the switching point detectioncircuit will be described by referring to FIGS. 2A to 2C.

[0045] Generally, when a channel width of the PMOS transistor becomestwice that of the NMOS transistor for an identical gate voltage in theMOS transistor, the same current flows at the channel. For example, whenthe channel width of the PMOS transistor is 10 μm and the channel widthof the NMOS transistor is 5 μm, the same current flows at each channelof the PMOS and NMOS transistors.

[0046] Accordingly, if the inverter is fabricated with which the channelwidth of the PMOS transistor becomes twice for that of the NMOStransistor, the output voltage thereof is switched at a half powersupply voltage.

[0047] Referring to FIG. 2A, when the first resistance R1 and the secondresistance R2 have the same resistance value, the reference voltage Vrefbecomes a half power supply voltage ½ VDD. At this time, if the firstCMOS inverter is fabricated to have channel widths of 8 μm and 5 μm forthe PMOS and NMOS transistors, respectively, the NMOS transistor MN1becomes dominant for the reference voltage Vref, which means a currentflowing in the NMOS transistor MN1 is higher than that of the PMOStransistor MP1, so that an output det_(—)1.6b of the first inverter 20becomes a logic low level signal. If the first CMOS inverter isfabricated to have channel widths of 12 μm and 5 μm for the PMOS andNMOS transistors, respectively, the PMOS transistor MP2 becomes dominantfor the reference voltage Vref, which means a current flowing in thePMOS transistor MP2 is higher than that of the NMOS transistor MN2, sothat an output det_(—)2.4b of the second inverter 30 becomes a logichigh level signal.

[0048] Considering an operation of the first CMOS inverter 20, if thefirst CMOS inverter 20 is fabricated identical to the a designedinverter, that is to say, the PMOS transistor MP1 is a ‘N’ condition andthe NMOS transistor MN1 is a ‘N’ condition, a waveform showing aswitching point may be a ‘PNNN’ waveform illustrated in FIG. 2B.

[0049] Also, if the MOS transistor is fabricated not identical to thedesigned MOS transistor, that is to say, the PMOS transistor MP1 isfabricated with a ‘S’ condition and the NMOS transistor MN1 isfabricated with a ‘F’ condition, a waveform of a switching point for thefirst CMOS inverter 20 will be ‘PSNF’ in FIG. 2B. On the contrary, ifthe PMOS transistor MP1 is fabricated with a ‘F’ condition and the NMOStransistor MN1 is fabricated with a ‘S’ condition, a waveform of theswitching point for the first CMOS inverter 20 will be ‘PFNS’ in FIG.2B.

[0050] Therefore, when the PMOS transistor MP1 is fabricated with a ‘F’condition and the NMOS transistor MN1 is fabricated with a ‘S’condition, an output of the first CMOS inverter 20 becomes a logic highlevel signal when the reference voltage Vref, which is VDD/2, isapplied. Therefore, the fabrication condition of the first CMOS inverter20 can be detected.

[0051] Hereinafter, considering an operation of the second CMOS inverter30, if the MOS transistors are fabricated identical to the designed MOStransistors, that is to say, the PMOS transistor MP2 is fabricated withan ‘N’ condition and the NMOS transistor MN2 is fabricated with a ‘P’condition, a waveform of a switching point for the second CMOS inverter30 will be ‘PNNN’ in FIG. 2C. Also, if the PMOS transistor MP2 isfabricated with a ‘F’ condition and the NMOS transistor MN2 isfabricated with a ‘S’ condition, a waveform of a switching point for thesecond CMOS inverter 30 will be ‘PFNS’ in FIG. 2C. On the contrary, ifthe PMOS transistor MP2 is fabricated with a ‘S’ condition and the NMOStransistor MN2 is fabricated with a ‘F’ condition, a waveform of aswitching point for the second CMOS inverter 30 will be ‘PFNS’ in FIG.2C.

[0052] Therefore, when the PMOS transistor MP2 is fabricated with a ‘S’condition and the NMOS transistor MN2 is fabricated with a ‘F’condition, an output of the second CMOS inverter 20 becomes a logic lowlevel signal when the reference voltage Vref, which is VDD/2, isapplied. Therefore, the fabrication condition of the second CMOSinverter 30 can be detected.

[0053]FIG. 3 is a diagram showing a logic table representing operationconditions of the switching point detection circuit in FIG. 2A accordingto fabrication conditions for the MOS transistor.

[0054] As shown, when the reference voltage is applied, if the PMOStransistor P_MOS is fabricated with a ‘F’ condition and the NMOStransistor N_MOS is fabricated with a ‘S’ condition, the outputdet_(—)1.6b of the first inverter 20 becomes a logic high level 11. Ifthe PMOS transistor P_MOS is fabricated with a ‘S’ condition and theNMOS transistor N_MOS is fabricated with a ‘F’ condition, the outputdet_(—)2.4b of the second inverter 30 becomes a logic low level when thereference voltage Vref is applied.

[0055] As utilizing the outputs of the first and second CMOS inverters20 and 30, variation of the switching point according to the fabricationconditions of the CMOS transistor can be detected.

[0056] The switching point detection circuit is configured by concerningtwo conditions as mentioned above in accordance with the preferredembodiment of the present invention. However, the switching pointdetection circuit can be also differently configured by adjusting thechannel width of the MOS transistor so that the PMOS transistor isfabricated with a ‘N’ condition and the NMOS transistor is fabricatedwith a ‘F’ condition.

[0057]FIG. 4 is a circuit diagram illustrating another switching pointdetection circuit capable of generating a different reference voltageVref.

[0058] As shown, a reference voltage generator 70 includes a fifth NMOStransistor MN5 whose gate and drain are coupled each other and a fifthPMOS transistor MP5 whose gate and drain are coupled each other. Thefifth NMOS transistor MN5 and the fifth PMOS transistor MP5 are coupledin series between the power supply voltage VDD and the ground voltageVSS. The difference between the switching point detection circuit inFIG. 4 and the switching point detection circuit in FIG. 2 is how thereference voltage is generated.

[0059] When the PMOS transistor MP5 is a ‘F’ condition and the NMOStransistor MN5 is an ‘S’ condition in the reference voltage generationunit 70, the reference voltage Vref level becomes lower than a VDD/2level. Therefore, if the PMOS and NMOS transistors MP6 and MN6 arefabricated with an ‘N’ condition in the first CMOS inverter 80,respectively, since the reference voltage Vref is lower than the VDD/2,there is an effect that the switching point waveform moves from ‘PNNN’to ‘PFNS’ in FIG. 2A. Accordingly, the first CMOS inverter 80 outputs asignal of a logic high level.

[0060] Also, when the PMOS transistor MP5 is an ‘S’ condition and theNMOS transistor MN5 is an ‘F’ condition in the reference voltagegeneration unit 70, the reference voltage level Vref becomes higher thanthe VDD/2 level. Therefore, if the PMOS and NMOS transistors MP7 and MN6are fabricated with an ‘N’ condition in the second CMOS inverter 90,respectively, since the reference voltage Vref is higher than the VDD/2,there is an effect that the switching point waveform moves from ‘PNNN’to ‘PSNF’ in FIG. 2C. Accordingly, the second CMOS inverter outputs asignal of a logic low level.

[0061]FIGS. 5 and 6 are circuit diagrams illustrating further anotherdisclosed switching point detection circuit.

[0062] Referring to FIG. 5, the switching point detection circuitincludes a reference voltage generation unit 40, a first CMOS inverter50 and a second CMOS inverter 60. The reference voltage generation unit40 includes a third resistance R3, a fourth resistance R4 and a fifthresistance R5, which are coupled in series between the power supplyvoltage VDD and the ground voltage VSS. The reference voltage generationunit 40 generates a first reference voltage Vref_U, which is a highervoltage than the VDD/2 and a second reference voltage Vref_D, which is alower voltage than the VDD/2. The first and second CMOS inverters 50 and60 have a switching point at the half power supply voltage VDD/2 and thefirst and second reference voltages Vref_U and Vref_D are applied asinput voltages thereof, respectively. The switching point detectioncircuit in FIG. 5 can detect the switching point variation according tofabrication conditions of the MOS transistors at the first and secondreference voltages Vref_U and Vref_D.

[0063] The first reference voltage Vref_U is generated at a common nodeof the third and fourth resistances and the second reference voltageVref_D is generated at a common node of the fourth and fifthresistances.

[0064] Since the PMOS transistors and the NMOS transistors configuringthe first and second inverters 50 and 60 are fabricated with a widthratio of 2:1, the switching point is formed at the half power supplyvoltage VDD/2. When the resistances R3, R4 and R5 have the sameresistance value, the first reference voltage Vref_U has a ⅔ VDD leveland the second reference voltage Vref_D has an ⅓ VDD level, so that thefirst CMOS inverter 50 outputs a signal of a logic low level and thesecond CMOS inverter 60 outputs a signal of a logic high level. Thevoltage level of ⅔ VDD or ⅓ VDD is not important. It is important thatthe reference voltages Vref_U and Vref_D have a higher and lower voltagelevel than the ½ VDD level, respectively.

[0065] If the PMOS transistor MP3 has a ‘F’ condition and the NMOStransistor MN3 has a ‘S’ condition in the first CMOS inverter 50, thefirst CMOS inverter 50 outputs a signal of a logic high level. If thePMOS transistor MP4 has an ‘S’ condition and the NMOS transistor MN4 hasan ‘F’ condition, the second CMOS inverter 60 outputs a signal of alogic low level. Therefore, as detecting the outputs of each inverter, amanufacturing condition can be notified.

[0066] Referring to FIG. 6, the third and fourth resistors are replacedwith transistors MN8 and MP8, respectively. The actual operation of theswitching point detection circuit in FIG. 6 is similar to that of theswitching point detection circuit of FIG. 5.

[0067]FIGS. 7A to 7D are circuit diagrams showing methods for variouslygenerating the reference voltage.

[0068] As shown, an external power supply voltage Vext is employed as anoperation voltage instead of the VDD in the switching point detectioncircuit shown in FIGS. 2A, 4 to 6.

[0069]FIGS. 8A and 8B are schematic diagrams illustrating switchingpoint detection circuit having a differential amplifier. Since theoutput signal of the switching point detection circuit is very weak, thedifferential amplifier is added to amplify the output of the disclosedswitching point detection circuit.

[0070] Referring to FIG. 8A, two differential amplifiers 220 and 230 areadded at output terminals of the switching point detection circuit inFIG. 2A or 4, respectively.

[0071] Referring to FIG. 8A, two differential amplifiers 320 and 330 areadded at output terminals, respectively, of the switching pointdetection circuit shown in FIG. 5 or 6.

[0072]FIGS. 8C to 8F are circuit diagrams illustrating the differentialamplifier commonly applied in FIGS. 8A and 8B. The reference voltagegenerated from the reference voltage generation unit, i.e., VREF, VREF_Uor VREF_D is applied to one input terminal and the output signal of theswitching point detection circuit, i.e., det_(—)1.6b or det_(—)2.4b isapplied to the other input terminal in the differential amplifier.

[0073]FIG. 9A is a circuit diagram showing a conventional input buffer.

[0074] As shown, the input buffer includes an input buffering unit 410,a delay unit 420, a latch 430 and a clock generator 440. The inputbuffering unit 410 receives an input signal A and the delay unit 420delays an output of the input buffering unit 410. The latch 430synchronizes an output signal of the delay unit 420 with a clock signalgenerated from the clock generator 440 and output an intern signal B.However, if the input buffer is configured as FIG. 9A, a voltage levelof the input signal may be varied according to a fabrication conditionof NMOS and PMOS transistors, so that operational reliability of thesemiconductor device may be deteriorated.

[0075]FIG. 9B is a circuit diagram illustrating an input buffer having adisclosed switching point detection circuit.

[0076] As shown, the input buffer capable of adjusting a switching pointby detecting a fabricating condition includes a switching pointdetection circuit consisting of a first CMOS inverter 491, in which anNMOS transistor is dominant for a reference voltage Vref and a secondCMOS inverter 492, in which a PMOS transistor is dominant for thereference voltage Vref. The input buffer further includes a bufferingunit 450 for receiving and buffering an input signal A, a delay unit 460for transmitting and delaying an output signal of the buffering unit 463in response to output signals of the first and second CMOS inverters 491and 492, a latch unit 470 for latching an output signal of the delayunit 460 and a clock generation unit 480 for inputting a clock signal tothe latch unit 470.

[0077] The delay unit 460 includes a first delay 461 for delaying theoutput signal of the buffering unit 450 by a first predetermined time, afirst multiplexer 462 for selectively outputting the output signal ofthe buffering unit 450 or an output signal of the first delay 461 inresponse to the output signal of the first CMOS inverter 491, a seconddelay for delaying an output signal of the first multiplexer 462 by asecond predetermined time, a third delay 464 for delaying an outputsignal of the second delay 463 and a second multiplexer 465 forselectively outputting the output signal of the second delay 463 or anoutput signal of the third delay 464. Herein, the reference voltage canbe generated with methods described in FIGS. 4 to 6.

[0078] Hereinafter, an operation of the input buffer illustrated in FIG.9B will be described. The reference voltage Vref is stably outputtedwith a half power supply voltage and the output signals of the firstCMOS inverter 491 are determined according to a fabrication condition ofthe NMOS transistor and PMOS transistor. A delay of the input signal Ais adjusted by selectively passing the first and three delays 461 and464 according to the output signals of the first and second CMOSinverters 491 and 492.

[0079] Accordingly, even though the fabrication condition of the MOStransistor is varied, an output signal for an input signal can beuniformly maintained, so that reliability of an operation of thesemiconductor device can be secured.

[0080]FIG. 10 is a circuit diagram for a semiconductor device having adisclosed switching point detection circuit.

[0081] As shown, the semiconductor device includes a switching pointdetection circuit, a first multiplexer 530, a second multiplexer 540, abuffering unit 550, a third CMOS inverter 560, a first pull-up unit 570and a second pull-up unit 580.

[0082] The switching point detection circuit includes a first CMOSinverter 510, in which an NMOS transistor is dominant for the referencevoltage, and a second inverter 520, in which a PMOS transistor isdominant for the reference voltage. The first multiplexer selectivelyoutputs a power supply voltage or an input signal A according to anoutput signal of the first CMOS inverter 510 and the second multiplexer540 selectively outputs a power supply voltage or an input signal Aaccording to an output signal of the second CMOS inverter 520. Thebuffering unit 550 receives the input signal A and the third CMOSinverter 560 inverts an output signal A_B of the buffering unit 550. Thefirst pull-up unit 570 performs a pull-up operation for an output of thethird inverter 560 according to an output signal of the firstmultiplexer 530 and the second pull-up unit 580 performs a pull-upoperation for an output of the third inverter 560 according to an outputsignal of the second multiplexer 540.

[0083] The first multiplexer 530 includes a first transfer gate TG6,which is turned on when the output signal of the first CMOS inverter 510is a first logic state, coupled to a power supply voltage and a secondtransfer gate TG7, which is turned on when the output signal of thefirst CMOS inverter 510 is a second logic state, coupled to the inputsignal A. The second multiplexer 540 includes a third transfer gate TG8,which is turned on when the output signal of the second CMOS inverter520 is a first logic state, coupled to a power supply voltage and afourth transfer gate TG9, which is turned on when the output signal ofthe second CMOS inverter 520 is a second logic state, coupled to theinput signal A.

[0084] The buffering unit 550 consists of a transfer gate TG5, which isalways turned on, for setting timing for transferring the input signalby the third CMOS inverter 560 and timing for operating the first andsecond pull-up units 570 and 580. Output signals of the first and secondCMOS inverter 510 and 520 are determined by a fabrication condition ofthe NMOS transistor and the PMOS transistor. Outputs of the first andsecond multiplexers 530 and 540 are determined by the output signals ofthe first and second CMOS inverters 510 and 520. The first and secondpull-up units 570 and 580 are operated in response to the output signalsof the first and second multiplexers 530 and 540.

[0085] An output waveform of the input signal A is determined by thefirst and second pull-up units 570 and 580. Accordingly, a stable outputsignal can be transmitted to an internal circuit without of afabrication condition of a MOS transistor.

[0086]FIG. 11 is a waveform illustrating an operation of thesemiconductor device in FIG. 10.

[0087] As shown, when the switching point detection circuit is notemployed according to the prior art, an output waveform B for an inputwaveform A is varied according to a fabrication condition of a MOStransistor, such as a waveform at a PFNS condition or a waveform at aPSNF condition shown in FIG. 11. However, when the switching pointdetection circuit is employed in accordance with the present invention,an output form for the input signal can be stabilized as shown in anoutput waveform, which the switching point is adjusted.

[0088]FIG. 12A is a circuit diagram illustrating a semiconductor device,in which a long line having a high load is coupled to an input signal ofthe input buffer, and FIG. 12B is a circuit diagram illustrating asemiconductor device, in which a long line having a high load is coupledto an output signal of the output buffer.

[0089] Generally, the semiconductor device is fabricated to have a longline at an input or an output of the input buffer in order to reduce anoise of the input signal. Since an operation of the high load islargely affected by a fabrication condition of the semiconductor,reliability of an operation of the semiconductor device is deteriorated.Therefore, as the variation according to the fabrication condition ofthe MOS transistor is adjusted by the disclosed switching pointdetection circuit, even if the fabrication condition of the MOStransistor is varied, a stable output signal for an input signal can berequired. Therefore, the operational reliability is not deteriorated.

[0090]FIG. 12C is a waveform showing operations of the semiconductordevices illustrated in FIGS. 12A and 12B.

[0091] As shown, when the switching point detection circuit is notemployed according to the prior art, an output waveform B for an inputwaveform A is varied according to a fabrication condition of a MOStransistor, such as a waveform at a PFNS condition or a waveform at aPSNF condition shown in FIG. 12C. However, when the disclosed switchingpoint detection circuit is employed, an output waveform for the inputsignal can be stabilized as shown in an adjusted output waveform

[0092] Accordingly, as the semiconductor device includes a disclosedswitching point detection circuit capable of detecting a fabricationcondition of the MOS transistor, an operational error can be reduced, sothat operational reliability of the semiconductor device can beimproved.

[0093] While the disclosed circuits and devices have been described withrespect to the particular embodiments, it will be apparent to thoseskilled in the art that various changes and modifications may be madewithout departing from the spirit and scope of this disclosure which islimited only by the following claims.

What is claimed is:
 1. A switching point detection circuit for detectinga switching point according to a fabrication condition of MOStransistor, the circuit comprising: a reference voltage generation unitfor generating a reference voltage; a first CMOS inverter, in which anNMOS transistor is dominant for the reference voltage, receiving thereference voltage; and a second CMOS inverter, in which a PMOStransistor is dominant for the reference voltage, receiving thereference voltage.
 2. The switching point detection circuit as recitedin claim 1, wherein, in the first and second CMOS inverters, thedominant transistor is determined by adjusting a channel length or achannel width of the NMOS transistor or PMOS transistor.
 3. Theswitching point detection circuit as recited in claim 1, wherein thereference voltage generation unit generates the reference voltage byusing resistances.
 4. The switching point detection circuit as recitedin claim 1, wherein the reference voltage generation unit comprises: anNMOS transistor, whose gate and drain are coupled to a power supplyvoltage; and a PMOS transistor, whose gate is coupled to a groundvoltage, coupling the NMOS transistor to the ground voltage.
 5. Theswitching point detection circuit as recited in claim 1, furthercomprising: a first differential amplifier receiving the referencevoltage and an output of the first CMOS inverter; and a seconddifferential amplifier receiving the reference voltage and an output ofthe second CMOS inverter.
 6. A switching point detection circuit fordetecting a switching point according to a fabrication condition of MOStransistor, the circuit comprising: a reference voltage generation unitfor generating a first reference voltage, which is higher than a halfpower supply voltage, and a second reference voltage, which is lowerthan a half power supply voltage; a first CMOS inverter receiving thefirst reference voltage, having a switching point at the half powersupply voltage; and a second CMOS inverter receiving the secondreference voltage and having a switching point at the half power supplyvoltage.
 7. The switching point detection circuit as recited in claim 6,wherein the reference voltage generation unit comprises first to thirdresistances coupled in series between the power supply voltage and aground voltage, wherein the first reference voltage is generated at ajunction node of the first resistance and the second resistance and thesecond reference voltage is generated at a junction node of the secondresistance and the third resistance.
 8. The switching point detectioncircuit as recited in claim 6, wherein the reference voltage generationunit comprises: an NMOS transistor, whose gate is coupled to a powersupply voltage; a resistance coupled to the NMOS transistor; and a PMOStransistor, whose gate is coupled to a ground voltage, coupled betweenthe resistance and the ground voltage, wherein the first referencevoltage is generated at a junction node of the NMOS transistor and theresistance and the second reference voltage is generated at junctionnode of the resistance and the PMOS transistor.
 9. The switching pointdetection circuit as recited in claim 6, further comprising: a firstdifferential amplifier receiving the first reference voltage and anoutput of the first CMOS inverter; and a second differential amplifierreceiving the second reference voltage and an output of the second CMOSinverter.
 10. A semiconductor device comprising: a buffering means forbuffering an input signal; a switching point detection means fordetecting switching point variation of a CMOS inverter according to afabrication condition of a MOS transistor; and a delay means fordelaying the input signal under control of the switching point detectionmeans.
 11. The semiconductor device as recited in claim 10, wherein theswitching point detection means comprises: a reference voltagegeneration unit for generating a reference voltage; a first CMOSinverter, in which an NMOS transistor is dominant for the referencevoltage, receiving the reference voltage; and a second CMOS inverter, inwhich a PMOS transistor is dominant for the reference voltage, receivingthe reference voltage.
 12. The semiconductor device as recited in claim10, wherein the switching point detection means comprises: a referencevoltage generation unit for generating a first reference voltage, whichis higher than a half power supply voltage, and a second referencevoltage, which is lower than a half power supply voltage; a first CMOSinverter receiving the first reference voltage, having a switching pointat the half power supply voltage; and a second CMOS inverter receivingthe second reference voltage and having a switching point at the halfpower supply voltage.
 13. The semiconductor device as recited in claim12, wherein the delay means comprises: a first delay for delaying theinput signal by a first predetermined time; a first multiplexer forselectively outputting an output signal of the buffering means or anoutput signal of the first delay according to an output of the firstCMOS inverter; a second delay for delaying an output signal of the firstmultiplexer by a second predetermined time; a third delay for delayingan output signal of the second delay; and a second multiplexer forselectively outputting the output signal of the second delay or anoutput signal of the third delay according to an output signal of thesecond CMOS inverter.
 14. A semiconductor device comprising: a switchingpoint detection means for detecting switching point variation of a CMOSinverter according to a fabrication condition of a MOS transistor,comprising a reference voltage generation unit for generating areference voltage; a first CMOS inverter, in which an NMOS transistor isdominant for the reference voltage, receiving the reference voltage; anda second CMOS inverter, in which a PMOS transistor is dominant for thereference voltage, receiving the reference voltage; a first multiplexerfor selectively outputting a power supply voltage or an input signalaccording to an output signal of the first CMOS inverter; a secondmultiplexer for selectively outputting a power supply voltage or aninput signal according to an output signal of the second CMOS inverter;a third CMOS inverter for inverting the input signal; a first pull-upmeans for performing a pull-up operation for an output of the third CMOSinverter according to an output signal of the first multiplexer; and asecond pull-up means for performing a pull-up operation for an output ofthe third CMOS inverter according to an output signal of the secondmultiplexer.
 15. The semiconductor device as recited in claim 14,wherein the third CMOS inverter receives the input signal through atransfer gate.
 16. The semiconductor device as recited in claim 14,wherein the first multiplexer includes: a first transfer gate, which isturned on when an output signal of the first CMOS inverter is a firstlogic state, coupled to a power supply voltage; and a second transfergate, which is turned on when an output signal of the first CMOSinverter is a second logic state, coupled to the input signal.
 17. Thesemiconductor device as recited in claim 14, wherein the firstmultiplexer comprises: a first transfer gate, which is turned on when anoutput signal of the second CMOS inverter is a first logic state,coupled to a power supply voltage; and a second transfer gate, which isturned on when an output signal of the second CMOS inverter is a secondlogic state, coupled to the input signal.
 18. A semiconductor memorydevice, comprising: a switching point detection means for detectingswitching point variation of a CMOS inverter according to a fabricationcondition of a MOS transistor, includes: a reference voltage generationunit for generating a first reference voltage, which is higher than ahalf power supply voltage, and a second reference voltage, which islower than a half power supply voltage; a first CMOS inverter receivingthe first reference voltage, having a switching point at the half powersupply voltage; and a second CMOS inverter receiving the secondreference voltage and having a switching point at the half power supplyvoltage; a first multiplexer for selectively outputting a power supplyvoltage or an input signal according to an output signal of the firstCMOS inverter; a second multiplexer for selectively outputting a powersupply voltage or an input signal according to an output signal of thesecond CMOS inverter; a third CMOS inverter for inverting the inputsignal; a first pull-up means for performing a pull-up operation for anoutput of the third CMOS inverter according to an output signal of thefirst multiplexer; and a second pull-up means for performing a pull-upoperation for an output of the third CMOS inverter according to anoutput signal of the second multiplexer.
 19. The semiconductor device asrecited in claim 18, further comprising a fourth CMOS inverter forinverting an output signal of the third CMOS inverter.
 20. Thesemiconductor device as recited in claim 18, wherein the firstmultiplexer comprises: a first transfer gate, which is turned on when anoutput signal of the first CMOS inverter is a first logic state, coupledto a power supply voltage; and a second transfer gate, which is turnedon when an output signal of the first CMOS inverter is a second logicstate, coupled to the input signal.
 21. The semiconductor device asrecited in claim 20, wherein the first multiplexer comprises: a firsttransfer gate, which is turned on when an output signal of the secondCMOS inverter is a first logic state, coupled to a power supply voltage;and a second transfer gate, which is turned on when an output signal ofthe second CMOS inverter is a second logic state, coupled to the inputsignal.